Static random access memory (SRAM) devices are usually employed in computer systems as cache memories in order to carry out data accessing operations between main memories such as dynamic random access memories (DRAM) and central processing units. Basically, central processing units include primary cache memories therein, and secondary cache memories are positioned at the outside of the central processing unit. As well known, SRAM devices are usually used in computer systems as cache memories. When such a SRAM is employed in the system as the secondary cache apparatus, there is an important and specific function therein that is called a depth expansion mode (or a bank operation mode of a memory system which includes at least two memory devices sharing data buses on a single integrated circuit board; each memory device is referred to as one bank therein). Data read from bank are transferred to the shared data buses after the other data read from the other bank was provided to the shared data buses, so that an output capacity therethrough can be figure out as being available of being expanded to a data structure of two times. Assuming that one of the bank (or one SRAM device) is designed to create a data capacity of 32 bits in one cycle time, the two bank operations make twice expanded data capacity of 64 bits.
During the bank operation mode, the first bank generates output data while the second bank is not being selected, or the first bank is non-selected while the second bank is selected to generate output data thereof. Such a alternative activations between two banks is repeatedly carried out during the bank operation mode for which each bank is changed from a selection state to a non-selection state, or from a non-selection state and a selection state. A bank forced into the non-selection state retains a high impedance, by which a section word line (or a row decoding path) thereof is not activated in order to make memory cells of the non-selected bank be not influenced from a data accessing operation with memory cells of the selected bank. Approximately, a rate of current consumption in the selected bank is generally up to .rect-hollow. through 1/5 of that in the selected bank.
FIG. 1 shows schematic configurations of a control logic and a section word line decoding, for the purpose of controlling the non-selected banks during the bank operation mode. As shown in FIG. 1, control logic circuit 100 receives control signals CS1B, CS2B, CS2, ADVB, ADSCB and ADSPB, and then generates non-selection signal DESELECTB which is applied to section word line decoder 120. A bank receiving the non-selection signal DESELECTB does not perform a write or a read operation. Section word line decoder 120 to select a section word line SWL is activated in the selection state, or not activated in the non-selection state, in response to non-selection signals DESELECTB generated from control logic circuit 100.
As non-selection signal DESELECTB is made from combining the control signals CS1B, CS2B, CS2, ADVB and ADSPB in a logical accessing, there is an speed limit in generating the non-selection signal. For instance, comparing the time until DESELECTB is generated after an address input, tDES, to the time until a main word line responds to a decoding non-selection information for itself, tMWL. FIG. 2A shows that tDES runs to about half of tMWL in an operating condition of a low frequency, while FIG. 2B shows that tDES terminates at the most end of tMWL in a high frequency operation mode. Since the section row decoder 120 responds to DESELECTB in order to activate section word line SWL, the generation time of DESELECTB, tDES, is an inevitable time element being consumed in addressing the section word line.
Therefore, when the bank operation mode puts a bank into the selection state from the non-selection state, tDES may cause tSWL to be delayed in a higher frequency operation system. As shown in FIG. 2B, nevertheless tMWL and tSWL become more shortened as an operating frequency is more higher, tDES retains a constant value. The constant-retained tDES even in a high frequency operating system would make tSWL be delayed as much as being occupied by tDES throughout the time lapsing period thereof. As a result, an activation of a selected word line is more later, and thereby there would be a poor margin for a write operation in a lower power supply, or a malfunction in writing. Furthermore, a mis-alignment between activation times of sense amplifiers and word lines causes a glitch on data output paths and a shift of clock access time.